LPC 2148 Clock Mechanism
LPC 2148 needs 2 clocks - one for its peripherals and the other for its CPU. CPU works faster at higher frequencies and peripherals need not be fast. The Peripheral clock - PCLK and CPU CLock - CCLK can get clock input from a PLL or from an external source directly. Configuration of PLL and VPB Divider must be the first things in list after a reset. If your UART or timers are giving any timing mismatch or sync problems, then this is the first place you have to look for mistakes.
Choosing and Configuring CCLK:
LPC 2148 has a mechanism to handle EMI due to high frequency propagations on circuit board. It comes with an inbuilt PLL which can multiply the input clock frequency by a factor decided by the programmer. The designer can choose a low frequency crystal and can get his LPC 2148 work at a higher frequency by configuring the PLL appropriately.
LPC 2148 has SFRs dedicated for this configuration. These SFRs are:
1. PLLCON
2. PLLCFG
3. PLLSTAT and
4. PLLFEED
1. PLLSTAT is a read only register. It provides the actual status(parameters set in) of PLL. Bits 0-4 are called MSEL[Multipler Select] and Bits 5,6 are called PSEL[PLL Divider Select] determine the Multiplier and Divider values set on PLL. These two parameters determine the PLL output clock values. Bit 8 is PLLE[PLL Enable] bit which is 1 when PLL is ON. This bit is cleared automatically in powerdown mode. Bit 9 is PLLC[PLL Connect] bit which is 1 when PLL is connected as clock source to the microcontroller. When either of PLLE and PLLC is 0, the PLL is not connnected to the Clock source and the CPU Clock is connected to the external clock source directly. Bit 10 is PLOCK which is 1 when PLL is locked to the requested/configured frequency and 0 otherwise.
2. PLLCON controls the PLL activation. The Bit 0 also called PLLE[PLL Enable] activates PLL when set to 1. This allows PLL to lock to the desired frequency requested. This bit is 0 by default. The Bit 1 also called PLLC[PLL Connect] when 1 outputs to the system (CPU) clock or CCLK. PLLE and PLLC when set to 1 output clock signals to the microcontroller.
3. PLLCFG is the PLL Configuration register which controls the PLL Multiplier and divider values. Bits 0-4 decide the Multiplier and are called MSEL bits. The Bits 5,6 decide the Divider of PLL and are called PSEL bits. The choice of Multiplier is made based on the frequency the CPU is expected to run.
Multiplier[M] = (Expected CPU Clock Frequency/External Oscillator Frequency) - 1
For example, if external clock is 12 MHz and the expected clock frequency is 60 MHz then M = (60/12) - 1 = 4
M can take a value of maximum of 5 in LPC 2148
The choice of Divider is made depending on the CPU clock CCLK operting frequency and the Maximun operating frequency allowed. Maximum operating frequency allowed is 156 to 320 MHz. Hence P can have any intergral value between (156/60/2)1.3 to (320/60/2)2.8. The number PSEL can be set is a power of 2 hence the most appropriate P value is 2.
4. PLL provides clock input to the CPU and hence its configuration affects the entire system. To avoid acceidental writes to this peripheral, LPC 2148 offers a protection mechanism. Any write to the PLLCON and PLLCFG registers is valid and takes effect only after a Feed Sequence is written on PLLFEED register. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The write operation must be in consequtive clock cycles i.e no interrupt must occur while the Feed Sequence is written to PLLFEED. If any feed values are incorrect or any of the sequence conditions are not met, the values written on PLLCON and PLLCFG registers will not take effect. The PLLSTAT values may differ from the PLLCON and PLLCFG values. This happens when the feed sequence is not properly executed and the PLL state is exactly refered by PLLSTAT register and not by PLLCON and PLLCFG registers. The settings in PLLCFG and PLLCON will take effect only after the next successful feed sequence.
Choosing and Configuring PCLK:
PCLK is controlled by VLSI Peripheral Bus DIVider[VPBDIV] register. VPBDIV determines the relation between CCLK and PCLK. I provides peripherals with desired clock derived from PLL/external Osclliator and it can also turn off the clock to peripherals in powerdown mode when peripherals donot need to run.
Bits 0,1 of VPBDIV determine the relation between CCLK and PCLK. For the following values of Bits 1-0, the PCLK and CCLK values are:
00 VPB bus clock is one fourth of the processor clock. PCLK = CCLK / 4.
01 VPB bus clock is the same as the processor clock. PCLK = CCLK.
10 VPB bus clock is one half of the processor clock. PCLK = CCLK / 2.
11 Reserved. If this value is written to the VPBDIV register, it has no effect (the previous setting is retained).
For more information refer sections 3.8 and 3.11 of UM10139(User Manual).
